Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
The drastic performance, flexibility and energy-efficiency requirements of embedded applications drive the System-on-Chip integration towards heterogeneous multiprocessor platforms. Electronic System Level (ESL) design methodologies and tools have emerged to tackle the challenges of such complex SoC designs prior to RTL and silicon availability. In particular SystemC based Transaction Level Modeling (TLM) has matured as a standards-based approach to model SoC platforms for the purpose of Software development, system integration and verification.
In response to the vast complexity of heterogeneous multi-processor platforms the "Architects View" is emerging as a new TLM use-case to address the architecture definition and application mapping by means of timing approximate transaction-level models.
Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.
From the reviews:
"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool ... . This book's scope and range of pragmatic ideas make it valuable for a wide audience. ... When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area ... . It should resonate with students, researchers, and practical designers ... ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)
著者 Rainer Leupers
著者 Tim Kogel
著者 Heinrich Meyr
Product type 本
寸法 297 x 210 mm
製品重量 1060 g